The present invention relates to an information processing apparatus for performing a speech recognition process and an image recognition process.
In recent years, increasing attention has been focused on information processing to which a neural network is applied in the field of information processing. The neural network was achieved in imitation of the structure of neurons provided in the brain of a living organization. Although a large number of processes in the neural network are implemented by conventional sequential calculators of von Neumann type, their processing speeds are extremely low. To solve the problem, attempts have been made lately to implement the neural network by means of dedicated electronic circuits.
Among methods of implementing the neural network with dedicated electronic circuits, there has been known such a method as disclosed in Japanese Laid-Open Patent Publication No. 2-236658, in which hardware is used in common by a time-division method so that the amount of hardware is not exponentially increased even if the number of neurons is increased in order to perform more complicated information processing in the neural network.
In the above conventional method of implementing the neural network, however, the structure of the network system that can be implemented by a single information processing apparatus is fixed, so that it is inappropriate for a single information processing apparatus to implement any information processing from the simplest to the most complicated, i.e., any network from the smallest to the largest. This is because, to implement any neural network from the smallest to the largest, it is necessary to conform the information processing apparatus to the specification of a large-scale neural network. In the case of implementing a small-scale neural network, redundant parts are increased accordingly.
Moreover, as the number of data sets to be inputted and the number of candidates to be selected increase, the number of cycles required for selection is increased, so that the total processing time becomes longer.
If an address is allocated to each neuron as in the conventional method, on the other hand, the network scale is limited by the bit width of the address. In the case where the addresses of neurons are outputted to their common bus, it is impossible to output a plurality of addresses at the same time, so that longer processing time is required in accordance with the number of learning neurons.
In the case where a plurality of information processing apparatus are juxtaposed to expand the network, any one of the information processing apparatus is selected so that data is inputted to or outputted from the selected apparatus. Hence, it is impossible to input a set of data simultaneously to all the information processing apparatus, nor is it possible to obtain data from all the information apparatus at the same time, so that problems such as the deterioration of processing efficiency arise.
As for learning efficiency, if input data the font of which has similar configuration, such as printed characters, is to be learned, a specific input signal becomes large. In learning the Hebb learning rule, e.g., only the weight coefficient of a specific synapse becomes large so as to dominate the firing of the corresponding output neuron. The synapse with a large weight coefficient exerts a large influence in recognizing unlearned input data with a large signal, resulting in wrong recognition. As a result, even if the number of learnings is increased, the recognition rate with respect to unlearned data is not improved.